1. Field of the Invention
This invention relates generally to interfacing modules in host or device adapters, and in particular to bus structures and methods for interconnecting modules within a multiple I/O bus interface integrated circuit.
2. Description of Related Art
Prior single chip host adapters have included a plurality of modules and an on-chip processor that controls operation of the modules. For example, U.S. Pat. No. 5,659,690, entitled xe2x80x9cProgrammably Configurable Host Adapter Integrated Circuit Including a RISC Processor,xe2x80x9d issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference, had an internal bus that coupled the various modules to a sequencer that included a RISC processor.
Specifically, a SCSI module 130 (FIG. 1), a sequencer 120, data FIFO memory circuit 160, a memory 140, and a host interface module 110 were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit 100 both by a host microprocessor 170 through a host adapter driver 165 and by sequencer 120. The internal chip I/O bus CIOBUS included (i) a source bus with separate eight bit address and data buses, (ii) a destination bus with separate eight bit address and data buses, and (iii) a plurality of control signal lines, i.e., a chip source read enable line CSREN-, a chip destination write enable line CDWREN-, and a bus busy line CRBUSY. Internal chip I/O bus CIOBUS supported high speed normal operations that were controlled by sequencer 320 as well as slower but extended operations during error recovery that were controlled by the host adapter driver using the host microprocessor.
The splitting of the internal chip I/O bus CIOBUS into source and destination buses allowed each sequencer instruction to be completed in a single sequencer clock cycle, as opposed to the multiple cycles needed on a shared bus. Further, in some cases, a write operation and a read operation were performed simultaneously over internal chip I/O bus CIOBUS.
One problem encountered in implementing such a host adapter with an internal chip I/O bus CIOBUS is including hardware logic on the chip which controls the number of bus clock cycles for a particular module to complete a transaction over the internal bus. The. predicted performance of a particular module is not known until late in the design process because the performance of the module is dependent upon resources on the chip that the module must use. Consequently, the hardware logic necessary to control the number of bus clock cycles cannot be designed until the design of all the modules is complete. This inhibits parallel design efforts of the complete chip and introduces delays in the time to market.
In addition, some circuits may perform somewhat differently from that predicted during design. Consequently, the hardware circuit that controls the number of bus clock cycles may not be adequate. This typically requires either fabrication of a new chip, or alternatively a software design around which permits operation of the module, but results in reduced performance. Typically, the software design around included a sequence of no operation instructions in the firmware for the on-chip sequencer. A method and structure are needed that eliminates the need for a separate centralized hardware circuit for each module to control the number of bus clock cycles required for a transaction over the bus.
A cooperative communication bus structure and method of operation of a cooperative communication bus structure, within an integrated circuit interfacing multiple I/O buses, are utilized to eliminate the prior art method of designing and building a centralized hardware circuit to control the number of bus clock cycles required for data transfers between particular modules. A novel internal communication bus includes a new plurality of control lines that permit each of a plurality of bus masters to control different transactions on the internal communication bus.
In addition, either a source module, a destination module, or both modules, which are used in a data transfer, signal over the internal communication bus to the bus master when additional time is needed to participate in the data transfer.
If either the source module, destination module or both modules require more time, the bus master, in response to the active stretch bus access signal or signals from the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Moreover, within a module, the lengthening of the bus access cycle may be limited to only those addresses that need more time. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module.
This invention eliminates the need for a separate hardware circuit that implements bus delays for transfers between each set of hardware modules. In addition, this invention simplifies the design and enhances the time to market, because the designer of the source module and/or destination module includes logic within the module, as described more completely below, to determine when the module is ready to initiate the data transfer. Consequently, the designer of the bus master circuit and other circuits within the integrated circuit does not have to make any allowances for the performance characteristics for each module that the bus master circuit and other circuits communicate with over the internal communication bus.
Hence, in an integrated circuit having a plurality of modules coupled to each other by an internal communication bus having a control bus, a method of this invention includes:
driving an active signal on a bus access cycle stretch line in the control bus by a module, in the plurality of modules, having a storage location addressed by a bus master during a bus access cycle; and
holding, after the active signal on the bus stretch line, a state of a signal on a data write enable line in the control bus by the bus master until the active signal on the bus access cycle stretch line is driven inactive by the module wherein the active signal on the bus access cycle stretch line causes the bus master to change a duration of the bus access cycle.
The module can be either a source module, or a destination module, and the state of the signal on the data write enable line is an inactive state in a first embodiment. In another embodiment, the state of the signal on the data write enable line is active.
When the addressed storage location comprises a single point address type memory, the module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned such that the full width of a data bus of the internal communication bus cannot be used in a data transfer, i.e., the internal expansion address is not aligned with a natural boundary of the data bus.
Thus, the method of this invention re-times an internal communication bus access cycle having a first period by generating an active bus re-time signal by a module used in the internal communication bus access cycle, and by changing the bus access cycle to a second period different from the first period by a module controlling the bus access cycle in response to the active bus re-time signal.